This invention relates generally to operational amplifiers and, more particularly, to an operational amplifier utilizing input junction field effect transistors (JFETs) which directly drive a current mirror circuit, and an output stage comprised solely of NPN devices.
Operational amplifiers are known which utilize input junction field effect transistors (JFETs) which directly drive a current mirror circuit. Furthermore, in order to simplify integrated circuit construction, achieve a higher frequency response, greater output swing, and reduce output stage emitter follower peaking and excess phase with capacitive loads, it has been found desirable to provide an operational output stage which incorporates only NPN transistors. Such an output stage is shown and described in U.S. Pat. No. 3,416,092.
Unfortunately, in a P-channel JFET operational amplifier utilizing an NPN output stage being developed by the assignee of the present invention, it was discovered that the device exhibited poor DC gain while driving a load (e.g. a 2K ohm load from 0 volts to minus 10 volts). It was discovered that this gain problem was caused by a voltage .DELTA.V.sub.BE across the base-emitter terminals of the output power NPN devices (which were caused by load current changes) being reflected to the drains of the input JFETs (i.e. approximately 55 mv). Due to the low output impedance of the JFETs (e.g. only 600K ohms) the 55 mv change caused the gain of the circuit to be seriously degraded.